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Author

  • Daisuke Saito, Toshiyuki Kobayashi, Hiroki Koga, Nicolo Ronchi*, Kaustuv Banerjee*, Yusuke Shuto, Jun Okuno, Kenta Konishi, Luca Di Piazza*, Arindam Mallik*, Jan Van Houdt*, Masanori Tsukamoto, Kazunobu Ohkuri, Taku Umebayashi, Takayuki Ezaki

Company

  • Sony Corporation

Venue

  • VLSI

Date

  • 2021

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Analog In-memory Computing in FeFET-based 1T1R Array for Edge AI Applications

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Abstract

Deep neural network (DNN) inference for edge AI requires low-power operation, which can be achieved by implementing massively parallel matrix-vector multiplications (MVM) in the analog domain on a highly resistive memory array. We propose a 1T1R compute cell (1T1R-cell) using a ferroelectric hafnium oxide-based FET (FeFET) and TiN/SiO 2 tunneling junction of MΩ resistor (MOR) for analog in-memory computing (AiMC). The MOR exhibited a tunneling current behavior and MΩ resistance. A 1T1R-cell array-level evaluation was also performed. A random access for writing with low write disturbance scheme was confirmed from the summation-DC-current output, and binaries were successfully classified into “T” and “L.” Based on the experimental results of our proposed 1T1R-cell, we obtained a state-of-the-art energy efficiency of 13700 TOPS/W including the periphery. Furthermore, we confirmed that a high inference accuracy can be obtained with our low-resistance-variability 1T1R-cell with a properly trained model.

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